#include "mid_pwm.h"
#include "app_key.h"
uint32_t cnt = 0;
void PWM0_Callback(void *device, uint32_t wpara, uint32_t lpara)
{
    if (wpara & PWM_INIT_CNTOF_Msk) /* Overflow interrupt determination */
    {

    }
    if (lpara & PWM_STR_CH0SF_Msk)  /* Channel 0 matches the interrupt determination */
    {

    }
    if (lpara & PWM_STR_CH1SF_Msk)  /* Channel 1 matches the interrupt determination */
    {

    }
}
/*!
 * @brief PWM2_Callback
 *        PWM2 interrupts user callback function
 *
 * @param[in] wpara: Overflow interrupt flag parameter
 *
 * @param[in] lpara: Channel matching interrupt flag parameter
 *
 * @return none
 */
void PWM2_Callback(void *device, uint32_t wpara, uint32_t lpara)
{
    if (wpara & PWM_INIT_CNTOF_Msk) /* Overflow interrupt determination */
    {

    }
    if (lpara & PWM_STR_CH2SF_Msk)  /* Channel 2 matches interrupt determination */
    {

    }
    if (lpara & PWM_STR_CH3SF_Msk)  /* Channel 3 matches interrupt determination */
    {

    }
}
/*!
 * @brief PWM1_Callback
 *        PWM1 interrupts user callback function
 *
 * @param[in] wpara: Overflow interrupt flag parameter
 *
 * @param[in] lpara: Channel matching interrupt flag parameter
 *
 * @return none
 */
void PWM1_Callback(void *device, uint32_t wpara, uint32_t lpara)
{
	cnt ++;
    if (wpara & PWM_INIT_CNTOF_Msk) /* Overflow interrupt determination */
    {
		PWM_SetChannelCountValue(PWM2, PWM_CH_3, 0x3E80/100*g_Q5010Parameters.ucLcPwmPercent);
    }
    if (lpara & PWM_STR_CH3SF_Msk)  /* Channel 0 matches the interrupt determination */
    {
		PWM_SetChannelCountValue(PWM2, PWM_CH_3, 0x3E80/100*(100 - g_Q5010Parameters.ucLcPwmPercent));
    }
 }
void Set_BlackLight_PwmDuty(uint8_t Duty)
{
	PWM_SetChannelCountValue(PWM0, PWM_CH_3, Duty * PWM0_MAX_VALUE / 100);
}
void PWM0_OutputIndependent_Init(void)
{
    PWM_ConfigType config;
    PWM_ModulationConfigType pwmConfig;
    PWM_IndependentChConfig independentChConfig[1];

    memset(&config, 0U, sizeof(config));
    memset(&pwmConfig, 0U, sizeof(pwmConfig));
    memset(&independentChConfig, 0U, sizeof(independentChConfig));

    GPIO_SetFunc(GPIOA, GPIO_PIN4, GPIO_FUN1);  /* PA4  PWM0_CH3 */


    independentChConfig[0].channel = PWM_CH_3;                        /* Independent output channel selection */
    independentChConfig[0].chValue = PWM0_CH3_VALUE;                  /* The channel matches the value and determines the duty cycle */
    independentChConfig[0].levelMode = PWM_HIGH_TRUE;                 /* Output level polarity after the channel matching value is reached */

    /* Channel output polarity, which affects the level after mask, the level after triggering fault control,
       and the level for deadzone insertion. Here, the polarity is configured to be high, that is, low output after mask */
    independentChConfig[0].polarity = PWM_OUTPUT_POLARITY_ACTIVE_HIGH;
    independentChConfig[0].interruptEn = ENABLE;                      /* The channel matches the interrupt enable bit */
    independentChConfig[0].initLevel = PWM_HIGH_LEVEL;                 /* Channel initial level configuration, which affects the level before channel matching after initialization */
    independentChConfig[0].triggerEn = DISABLE;                       /* When the channel value is matched, the trigger signal can be generated for the trigger source of other modules */

    pwmConfig.countMode = PWM_UP_DOWN_COUNT;            /* PWM counter mode Settings */
    pwmConfig.independentChannelNum = 1;                /* Number of independent channels */
    pwmConfig.combineChannelNum = 0;                    /* Combined channel logarithm */
    pwmConfig.independentChConfig = independentChConfig;/* Independent channel configuration struct assignment */
    pwmConfig.combineChConfig = NULL;                   /* Combined channel configuration struct assignment */
    pwmConfig.initChOutputEn = ENABLE;                  /* Initialize the channel output enable bit */
    pwmConfig.initTriggerEn = DISABLE;                  /* The PWM initial value triggers the enable bit */

    config.mode = PWM_MODE_MODULATION;     /* PWM mode configuration */
    config.initModeStruct = &pwmConfig;    /* Different modes initialize configuration struct assignments accordingly */
    config.clkSource = PWM_CLK_SOURCE_APB; /* PWM clock source selection */
    config.clkPsc = PWM0_CLK_PSC - 1;      /* Clock division factor */
    config.initValue = 0;                  /* Initial count value */
    config.maxValue = PWM0_MAX_VALUE;      /* Maximum count value. Determines the output waveform frequency */
    config.overflowInterrupEn = DISABLE;    /* Overflow interrupts the enable bit */
    config.cntOverflowFreq = 0;            /* The frequency at which overflow interrupts are generated, 0 means that each overflow produces an interrupt */
    config.interruptEn = DISABLE;           /* PWM total interrupt enable bit */
    config.callback = PWM0_Callback;       /* PWM interrupts user callback function */

    PWM_Init(PWM0, &config);
}

void PWM2_OutputCombine_Init(void)
{
#if 0
    PWM_ConfigType config;
    PWM_ModulationConfigType pwmConfig;
    PWM_CombineChConfig combineChConfig[1];

    memset(&config, 0U, sizeof(config));
    memset(&pwmConfig, 0U, sizeof(pwmConfig));
    memset(&combineChConfig, 0U, sizeof(combineChConfig));
	
	GPIO_SetFunc(GPIOA, GPIO_PIN10, GPIO_FUN1);  /* PA10  PWM2_CH3 */
    GPIO_SetFunc(GPIOA, GPIO_PIN11, GPIO_FUN1);  /* PA11  PWM2_CH2 */

    combineChConfig[0].pairChannel = PWM_CH_2;             /* Combined output channel selection, here CH2 and CH3 are combined, so CH2 is selected */
    combineChConfig[0].ch1stValue = PWM2_MAX_VALUE >> 1;   /* Channel n match value */
    combineChConfig[0].ch2ndValue = PWM2_MAX_VALUE >> 1;   /* Channel n+1 match value */
    combineChConfig[0].levelMode = PWM_HIGH_TRUE;          /* Output level polarity after reaching the first matching value */
    combineChConfig[0].deadtimeEn = ENABLE;                /* Dead zone insertion enable bit */
    combineChConfig[0].deadtime = 32;                      /* Dead time value, dead time function is only valid in combined mode */
    combineChConfig[0].deadtimePsc = PWM_DEADTIME_DIVID_1; /* Dead time clock divider */
    combineChConfig[0].complementEn = ENABLE;              /* The complementary output enable bit */
    combineChConfig[0].ch1stMatchDir = PWM_MATCH_DIR_UP;   /* Channel n matches the point effective direction and is only valid in up-down counting mode */
    combineChConfig[0].ch2ndMatchDir = PWM_MATCH_DIR_DOWN; /* Channel n+1 matches the point effective direction and is only valid in up-down counting mode */

    /* Channel output polarity, which affects the level after mask, the level after triggering fault control,
       and the level for deadzone insertion. Here, the polarity is configured to be high, that is, low output after mask */
    combineChConfig[0].ch1stPolarity = PWM_OUTPUT_POLARITY_ACTIVE_HIGH;
    combineChConfig[0].ch2ndPolarity = PWM_OUTPUT_POLARITY_ACTIVE_HIGH;

    combineChConfig[0].ch1stInterruptEn = DISABLE;         /* Channel n matches the interrupt enable bit */
    combineChConfig[0].ch2ndInterruptEn = DISABLE;         /* Channel n+1 matches the interrupt enable bit */
    combineChConfig[0].ch1stInitLevel = PWM_LOW_LEVEL;     /* Channel n initial level configuration, which affects the level before channel matching after initialization */
    combineChConfig[0].ch2ndInitLevel = PWM_LOW_LEVEL;     /* Channel n+1 initial level configuration, which affects the level before channel matching after initialization */
    combineChConfig[0].ch1stTriggerEn = DISABLE;           /* After matching the channel values, trigger signals can be generated for other modules */
    combineChConfig[0].ch2ndTriggerEn = DISABLE;           /* After matching the channel values, trigger signals can be generated for other modules */


    pwmConfig.countMode = PWM_UP_DOWN_COUNT;               /* PWM counter mode Settings */
    pwmConfig.independentChannelNum = 0;                   /* Number of independent channels */
    pwmConfig.combineChannelNum = 1;                       /* Combined channel logarithm */
    pwmConfig.independentChConfig = NULL;                  /* Independent channel configuration struct assignment */
    pwmConfig.combineChConfig = combineChConfig;           /* Combined channel configuration struct assignment */
    pwmConfig.initChOutputEn = ENABLE;                     /* Initialize the channel output enable bit */
    pwmConfig.initTriggerEn = DISABLE;                     /* The PWM initial value triggers the enable bit */

    config.mode = PWM_MODE_MODULATION;            /* PWM mode configuration */
    config.initModeStruct = &pwmConfig;           /* Different modes initialize configuration struct assignments accordingly */
    config.clkSource = PWM_CLK_SOURCE_APB;        /* PWM clock source selection */
    config.clkPsc = PWM2_CLK_PSC - 1;             /* Clock division factor */
    config.initValue = 0;                         /* Initial count value */
    config.maxValue = PWM2_MAX_VALUE;             /* Maximum count value. Determines the output waveform frequency */
    config.overflowInterrupEn = ENABLE;           /* Overflow interrupts the enable bit */
    config.cntOverflowFreq = 0;                   /* The frequency at which overflow interrupts are generated, 0 means that each overflow produces an interrupt */
    config.interruptEn = ENABLE;                  /* PWM total interrupt enable bit */
    config.callback = PWM2_Callback;              /* PWM interrupts user callback function */

    PWM_Init(PWM2, &config);
#endif
}
void LC_PWM_OutputIndependent_Init(void)
{
    PWM_ConfigType config;
    PWM_ModulationConfigType pwmConfig;
    PWM_IndependentChConfig independentChConfig[1];

    memset(&config, 0U, sizeof(config));
    memset(&pwmConfig, 0U, sizeof(pwmConfig));
    memset(&independentChConfig, 0U, sizeof(independentChConfig));

    GPIO_SetFunc(GPIOB, GPIO_PIN7, GPIO_FUN1);          /* PB7 PWM1_CH3 */

    independentChConfig[0].channel = PWM_CH_3;          /* Independent output channel selection */
    independentChConfig[0].chValue = PWM1_CH3_VALUE - 1;/* The channel matches the value and determines the duty cycle */
    independentChConfig[0].levelMode = PWM_HIGH_TRUE;   /* Output level polarity after the channel matching value is reached */

    /* Channel output polarity, which affects the level after mask, the level after triggering fault control,
       and the level for deadzone insertion. Here, the polarity is configured to be high, that is, low output after mask */
    independentChConfig[0].polarity = PWM_OUTPUT_POLARITY_ACTIVE_HIGH;
    independentChConfig[0].interruptEn = ENABLE;        /* The channel matches the interrupt enable bit */
    independentChConfig[0].initLevel = PWM_LOW_LEVEL;   /* Channel initial level configuration, which affects the level before channel matching after initialization */
    independentChConfig[0].triggerEn = DISABLE;         /* When the channel value is matched, the trigger signal can be generated for the trigger source of other modules */

    pwmConfig.countMode = PWM_UP_COUNT;                 /* PWM counter mode Settings */
    pwmConfig.independentChannelNum = 1;                /* Number of independent channels */
    pwmConfig.combineChannelNum = 0;                    /* Combined channel logarithm */
    pwmConfig.independentChConfig = independentChConfig;/* Independent channel configuration struct assignment */
    pwmConfig.combineChConfig = NULL;                   /* Combined channel configuration struct assignment */
    pwmConfig.initChOutputEn = ENABLE;                  /* Initialize the channel output enable bit */
    pwmConfig.initTriggerEn = DISABLE;                  /* The PWM initial value triggers the enable bit */

    config.mode = PWM_MODE_MODULATION;     /* PWM mode configuration */
    config.initModeStruct = &pwmConfig;    /* Different modes initialize configuration struct assignments accordingly */
    config.clkSource = PWM_CLK_SOURCE_APB; /* PWM clock source selection */
    config.clkPsc = PWM1_CLK_PSC - 1;      /* Clock division factor */
    config.initValue = 0;                  /* Initial count value */
    config.maxValue = PWM1_MAX_VALUE - 1;  /* Maximum count value. Determines the output waveform frequency */
    config.overflowInterrupEn = ENABLE;    /* Overflow interrupts the enable bit */
    config.cntOverflowFreq = 0;            /* The frequency at which overflow interrupts are generated, 0 means that each overflow produces an interrupt */
    config.interruptEn = ENABLE;           /* PWM total interrupt enable bit */
    config.callback = PWM1_Callback;       /* PWM interrupts user callback function */

    PWM_Init(PWM1, &config);
	
	memset(&config, 0U, sizeof(config));
    memset(&pwmConfig, 0U, sizeof(pwmConfig));
    memset(&independentChConfig, 0U, sizeof(independentChConfig));

    GPIO_SetFunc(GPIOA, GPIO_PIN10, GPIO_FUN1);  /* PA10  PWM2_CH3 */

    independentChConfig[0].channel = PWM_CH_3;                        /* Independent output channel selection */
    independentChConfig[0].chValue = PWM2_CH3_VALUE-1;                  /* The channel matches the value and determines the duty cycle */
    independentChConfig[0].levelMode = PWM_HIGH_TRUE;                 /* Output level polarity after the channel matching value is reached */

    /* Channel output polarity, which affects the level after mask, the level after triggering fault control,
       and the level for deadzone insertion. Here, the polarity is configured to be high, that is, low output after mask */
    independentChConfig[0].polarity = PWM_OUTPUT_POLARITY_ACTIVE_HIGH;
    independentChConfig[0].interruptEn = DISABLE;                      /* The channel matches the interrupt enable bit */
    independentChConfig[0].initLevel = PWM_LOW_LEVEL;                 /* Channel initial level configuration, which affects the level before channel matching after initialization */
    independentChConfig[0].triggerEn = DISABLE;                       /* When the channel value is matched, the trigger signal can be generated for the trigger source of other modules */

    pwmConfig.countMode = PWM_UP_COUNT;            /* PWM counter mode Settings */
    pwmConfig.independentChannelNum = 1;                /* Number of independent channels */
    pwmConfig.combineChannelNum = 0;                    /* Combined channel logarithm */
    pwmConfig.independentChConfig = independentChConfig;/* Independent channel configuration struct assignment */
    pwmConfig.combineChConfig = NULL;                   /* Combined channel configuration struct assignment */
    pwmConfig.initChOutputEn = ENABLE;                  /* Initialize the channel output enable bit */
    pwmConfig.initTriggerEn = DISABLE;                  /* The PWM initial value triggers the enable bit */

    config.mode = PWM_MODE_MODULATION;     /* PWM mode configuration */
    config.initModeStruct = &pwmConfig;    /* Different modes initialize configuration struct assignments accordingly */
    config.clkSource = PWM_CLK_SOURCE_APB; /* PWM clock source selection */
    config.clkPsc = PWM2_CLK_PSC - 1;      /* Clock division factor */
    config.initValue = 0;                  /* Initial count value */
    config.maxValue = PWM2_MAX_VALUE-1;      /* Maximum count value. Determines the output waveform frequency */
    config.overflowInterrupEn = DISABLE;    /* Overflow interrupts the enable bit */
    config.cntOverflowFreq = 0;            /* The frequency at which overflow interrupts are generated, 0 means that each overflow produces an interrupt */
    config.interruptEn = DISABLE;           /* PWM total interrupt enable bit */
    config.callback = PWM2_Callback;       /* PWM interrupts user callback function */

    PWM_Init(PWM2, &config);
}

/*!
 * @brief PWM2_OutputIndependent_Init
 *        The PWM2 module is initialized, and PWM2_CH0, PWM2_CH2, and PWM2_CH3 are configured in independent channel output, up/down count mode.
 *        The frequency was 20KHz with a CH0 duty cycle of 20%, CH2 duty cycle of 40%, and CH3 duty cycle of 60%
 *
 * @param[in] none
 *
 * @return none
 */

